The present technology relates to a memory device and to techniques for operating a memory device.
Recently, ultra high density storage devices have been proposed using a three-dimensional (3D) stacked memory structure. One example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture which comprises a stack of alternating conductive and dielectric layers. A memory hole is formed in the stack and a NAND string is then formed by filling the memory hole with materials including a charge-trapping layer. A straight NAND string extends in one memory hole, while a pipe- or U-shaped NAND string (P-BiCS) includes a pair of vertical columns of memory cells which extend in two memory holes and which are joined by a bottom back gate. Control gates of the memory cells and of select gate transistors are provided by the conductive layers.
However, various challenges are presented in operating such memory devices.
In a comparative sensing operation, FIGS. 10A, 10B, 10C, 10D, 10E, 10F, 10G and 10H, depicts plots, versus time, of a selected word line voltage, an unselected word line voltage, a selected SGD select gate voltage, a selected SGS select gate voltage, an unselected SGD select gate voltage, an unselected SGS select gate voltage, a bit line voltage and a source line voltage, respectively.
In the first sensing operation of FIG. 9A, FIGS. 11A, 11B, 11C, 11D, 11E, 11F, 11G and 11H, depicts plots, versus time, of a selected word line voltage, an unselected word line voltage, a selected SGD select gate voltage, a selected SGS select gate voltage, an unselected SGD select gate voltage, an unselected SGS select gate voltage, a bit line voltage and a source line voltage, respectively.
In the second and third sensing operation of FIG. 9B, FIGS. 12A, 12B, 12C, 12D, 12E, 12F, 12G and 12H, depicts plots, versus time, of a selected word line voltage, an unselected word line voltage, a selected SGD select gate voltage, a selected SGS select gate voltage, an unselected SGD select gate voltage, an unselected SGS select gate voltage, a bit line voltage and a source line voltage, respectively.
In the fourth sensing operation of FIG. 9C, FIGS. 13A, 13B, 13C, 13D, 13E, 13F, 13G and 13H, depicts plots, versus time, of a selected word line voltage, an unselected word line voltage, a selected SGD select gate voltage, a selected SGS select gate voltage, an unselected SGD select gate voltage, an unselected SGS select gate voltage, a bit line voltage and a source line voltage, respectively.
FIG. 14A depicts a plot of a channel voltage (Vch) of a NAND string versus channel position, in a physical model of a NAND string in which a channel portion under a selected word line is non-conductive.
FIG. 14B depicts a plot of Vch versus channel position when the word line voltages are ramped down concurrently with select gates, resulting in a large channel gradient which causes read disturb, consistent with the physical model of FIG. 14A.
FIG. 14C depicts a plot of Vch versus channel position, in a physical model of a NAND string having trapped electrons in a sensing operation.
FIG. 14D depicts a plot of Vch versus channel position, when a ramp down of the word line voltages occurs before the ramp down of the select gates, allowing electrons to escape from the channel.
FIG. 15A depicts a plot of Vch versus channel position, where memory cells in the erased state are between a selected memory cell and the driven end of a NAND string, allowing a voltage at the driven end to extend up to a channel portion of the selected memory cell, resulting in a large channel gradient.
FIG. 15B depicts a plot of Vch versus channel position, where a memory cell in the C state is between a selected memory cell and the driven end of a NAND string, preventing a voltage at the driven end from extending up to a channel portion of the selected memory cell, resulting in a smaller channel gradient compared to FIG. 15A.
FIG. 15C depicts a plot of Vch versus channel position before the word line voltages are ramped down in a sensing operation, where Vth=5 V and Vwl_sel=8 V for a memory cell connected to the selected word line, as a contrast to FIG. 14A in which Vwl_sel=3 V.
FIG. 15D follows FIG. 15C and depicts Vch versus channel position when voltages of a predefined subset of adjacent edge word lines are ramped down together according to the 2nd sensing operation of FIG. 12A-12H.
FIG. 15E follows FIG. 15C, and is an alternative to FIG. 15D, where voltages of a predefined subset of non-adjacent edge word lines are ramped down together according to the 2nd sensing operation of FIG. 12A-12H.